Fractional-N frequency synthesizers are phase-locked-loops (PLL) capable of generating output signals having frequencies that can be a non-integer multiple of a reference frequency. One popular technique involves digital encoding such as sigma-delta modulation and is commonly referred to as sigma-delta (ΣΔ) fractional-N synthesis.
FIG. 1 illustrates a high-level block diagram of a conventional sigma-delta fractional-N synthesis circuit 100. The circuit generally takes the form of a PLL that employs an input reference signal source 102 having a frequency Fref that is fed to one input of a phase frequency detector 104. A second input of the detector receives a signal from a frequency divider 106. The divider responds to control signals generated by a sigma-delta modulator 108 and also receives the output signal Fout from a voltage-controlled oscillator VCO 112 that modifies it's output based on the level of error in the output of the phase detector 104 and a charge pump 109. A loop filter 110 removes the high frequency noise generated as the sigma-delta modulator randomizes spurious energy.
FIG. 2 shows a commonly used frequency divider topology 200, that includes a dual modulus prescaler 202. The dual modulus prescaler is a programmable frequency divider that can divide an input signal of a given frequency by an integer N or N+1, where for ease of implementation, N is usually a power of 2. In the example of FIG. 2, N is 4. The input of the prescaler 202 CKin is connected to a high frequency periodic source which is usually the VCO, assumed in this example to run at approximately 4 GHz. The prescaler 202 generates an output CKpr that is connected to a programmable counter 204. With a divisor of N=4, the output CKOUTi is generally a signal exhibiting a frequency of 1 GHz.
The programmable counter 204 is programmed by two integer parameters P and S. P represents the total number of pulses of signal CKpr in one division cycle. At the end of every division cycle, the PS counter asserts an output signal pulse CKOUTi. During S of these P cycles, the PS Counter 204 programs the prescaler 202 to divide by N+1 (or 5 in this example) by asserting an appropriate control signal called DIV5. During the remaining (P−S) pulses the prescaler divides the input clock by N (4 in this case). Finally, the total number of pulses of the high frequency source (VCO pulses) in a division cycle is S(N+1)+(P−S)*N=N*P+S Any division ratio N*P+S greater than N*(N+1) is achievable by selecting appropriate values of P and S. The programmed value of S is between 0 and N−1. The output of the PS counter 204 CKOUTi can be retimed by a flip-flop element 208 that is clocked by CKpr to generate a cleaner output CKOUT, thus eliminating the noise introduced by the PS counter. Signal CKOUT is signal CKOUTi delayed by one period of clock CKpr. Clock CKOUT is the feedback clock connected the second input of the phase frequency detector 104 of FIG. 1.
FIG. 3 shows a timing chart that illustrates the various timing relationships between signals CKpr, DIV5 and CKOUT for an example division of 27. In this case N=4, S=3 and P=6. The PS counter 204 is clocked by the rising edge of CKpr. With the rising edge of the clock at time tn, the CKOUT signal of the previous cycle is generated. The programmed P and S values are sampled by the PS counter 204 at the same time. The DIV5 signal is read by the prescaler 202 at every rising edge of the prescaler output CKpr and the prescaler functions accordingly during this period dividing by 4 or 5 until the next rising edge of CKpr when DIV5 is sampled again. Since the values of P and S are unknown before tn and S=0 is a possibility, the DIV5 signal is always low in the first period of CKpr after tn and the prescaler always divides by 4. Based on the value of S, the prescaler 202 divides the high frequency input clock signal by 5 for the next 0 to 3 periods.
While the conventional topologies and methods described above work well for their intended applications, the division ratio of the frequency divider 106 is modulated by the output of the sigma-delta modulator 108 and is different in every cycle. Because of the different switching patterns, different disturbances on the power supply or other relatively slow nodes inside the divider can result in different delays in the feedback signal. This modulated delay is undesirable because it creates nonlinearity in the sigma delta modulation and can fold high frequency quantization noise inside the loop bandwidth. This effect often results in degraded overall noise performance for the synthesizer.